D Flip-Flop from Logic Gates

Build a level-sensitive D latch using basic AND and NOT gates—understand how flip-flops work from the inside!

Overview

While dedicated flip-flop ICs are convenient, understanding how they're built from basic gates reveals the elegant logic behind digital memory. In this project, you'll construct a D latch (level-sensitive flip-flop) using AND gates and NOT gates. When the Enable input is HIGH, the output follows the Data input. When Enable goes LOW, the output "latches" and holds the last value—creating memory from pure combinational logic! This is the foundation of all sequential circuits.

Components Needed

  • 1x CD4081 IC (Quad AND Gate)
  • 1x SN74HC04 IC (Hex Inverter)
  • 2x LED
  • 2x Switch
  • severalx Wires

Instructions

  1. Gather Your Components

    Collect all materials: the CD4081 quad AND gate IC, SN74HC04 hex inverter (NOT gate) IC, two LEDs, two switches, wires, breadboard, and 5V power supply. The CD4081 provides four AND gates, and the SN74HC04 provides six inverters—we'll use a subset of each.

  2. Identify the CD4081 AND Gate IC

    The CD4081 is a 14-pin IC containing four independent 2-input AND gates. Pin 1 and 2 are inputs to Gate 1, Pin 3 is its output. Pins 5-6-4 form Gate 2, Pins 8-9-10 form Gate 3, and Pins 12-13-11 form Gate 4. Pin 7 is VSS (ground), Pin 14 is VDD (power). The notch marks Pin 1.

  3. Identify the SN74HC04 Inverter IC

    The SN74HC04 is a 14-pin IC containing six independent NOT gates (inverters). Pin 1 is input to Inverter 1, Pin 2 is its output. The pattern continues: 3-4, 5-6, 9-8, 11-10, 13-12 for the remaining inverters. Pin 7 is ground, Pin 14 is Vcc.

  4. Build the D Latch Circuit

    Place both ICs on the breadboard. Connect power (Pin 14 to 5V, Pin 7 to GND) for both chips. Build the latch: use one AND gate with inputs from Data and Enable, another AND gate with inputs from NOT(Data) and Enable. The outputs of these AND gates feed into a cross-coupled NOR latch built from two more AND gates and inverters. Connect switches for Data (top) and Enable (bottom), and LEDs to the Q and Q̄ outputs.

  5. Initial State: Both Switches Off

    Start with both switches in the OFF position. Data = 0, Enable = 0. The latch is disabled, so it holds whatever state it powered up in. The LEDs show Q=0, Q̄=1 (output 01 pattern).

  6. Data HIGH, Enable Still LOW

    Move the Data switch (top) to ON. Enable is still LOW, so the latch remains locked—the output doesn't change. The AND gates that pass data are blocked because Enable = 0.

  7. Enable the Latch with Data LOW

    Move Data back to OFF, then move Enable (bottom switch) to ON. The latch is now enabled and "transparent." Since Data = 0, the output shows Q=0, Q̄=1. The output is following the input.

  8. Change Data While Enabled

    With Enable still HIGH, move Data to ON. Watch the output change immediately to Q=1, Q̄=0! While enabled, the latch is transparent—any change on Data appears at the output. This is different from edge-triggered flip-flops.

  9. Disable the Latch: Data is Latched!

    Move Enable to OFF while keeping Data HIGH. The output is now "latched"—it holds Q=1 even though Enable is LOW. The data has been captured and stored!

  10. Verify Data is Truly Stored

    Now move the Data switch to OFF. The output remains at Q=1! Even though Data is now 0, the latch is disabled and ignoring input changes. This is the memory function—the latch remembers the last value present when Enable went LOW.

Challenges

  • Draw the schematic of your circuit and trace the signal path for both enabled and disabled states
  • Build a master-slave D flip-flop by adding a second latch with an inverted enable
  • Add indicator LEDs to intermediate nodes to visualize how signals propagate
  • Try building an SR latch first using just NAND or NOR gates
  • Compare the timing behavior of this latch to the SN74LS74 flip-flop from the previous project