Memory Interface

Build a memory interface with address decoding and data bus—connecting your CPU to RAM and ROM.

Overview

A CPU needs memory—ROM for program code and RAM for data. The memory interface handles address decoding (selecting the right chip), data bus management (reading/writing), and timing. This project connects multiple memory chips to a shared address and data bus.

Components Needed

  • 1x 28C16 EEPROM or similar
  • 1x 6116 SRAM or similar
  • 1x SN74HC139 IC (Address Decoder)
  • 1x SN74HC245 IC (Bus Transceiver)
  • 8x LED
  • severalx Wires

Instructions

  1. Plan the Memory Map

    Decide how to divide address space: e.g., 0x00-0x7F for ROM (128 bytes), 0x80-0xFF for RAM (128 bytes). The MSB selects ROM vs RAM.

  2. Wire Address Decoding

    Use the 74HC139 to decode the upper address bit(s). Connect outputs to chip select pins of ROM and RAM.

  3. Connect Data Bus

    Wire data pins of both memory chips to a shared 8-bit bus. Add the 74HC245 transceiver for direction control and buffering.

  4. Test Read/Write

    Pre-program some values into the EEPROM. Read them by setting addresses. Test RAM by writing and reading back values.

Challenges

  • Add more memory chips to expand address space
  • Implement memory-mapped I/O for peripherals
  • Add wait states for slower memory
  • Build a stack pointer for stack memory access