Rising Edge D Flip-Flop with SN74LS74

Build a D flip-flop circuit using the SN74LS74 IC—learn how digital memory captures and holds data on the rising clock edge!

Overview

The D flip-flop is the fundamental building block of digital memory and sequential logic. Unlike combinational circuits where outputs depend only on current inputs, sequential circuits like flip-flops "remember" past states. The SN74LS74 contains two independent rising-edge triggered D flip-flops. In this project, you'll discover how data is captured only at the precise moment the clock signal transitions from LOW to HIGH—the rising edge. This edge-triggering behavior is what makes synchronous digital systems possible, from simple counters to complex CPUs.

Components Needed

  • 1x SN74LS74 IC
  • 2x LED
  • 2x Switch
  • severalx Wires

Instructions

  1. Gather Your Components

    Collect all materials: the SN74LS74 dual D flip-flop IC, two LEDs (for Q and Q̄ outputs), two switches (for Data and Clock inputs), wires, breadboard, and 5V power supply. The IC contains two independent flip-flops, but we'll use just one for this experiment.

  2. Identify the SN74LS74 IC

    The SN74LS74 is a 14-pin IC containing two D flip-flops. Pin 1 is Clear (active low), Pin 2 is D input, Pin 3 is Clock, Pin 4 is Preset (active low), Pin 5 is Q output, Pin 6 is Q̄ (not Q) output, Pin 7 is GND, and Pins 8-13 repeat for the second flip-flop. Pin 14 is Vcc. The notch or dot marks Pin 1.

  3. Build the Circuit

    Place the IC on the breadboard straddling the center channel. Connect Pin 14 to 5V and Pin 7 to ground. Tie Pin 1 (Clear) and Pin 4 (Preset) to 5V to disable these control inputs. Connect one switch to Pin 2 (D input) and another to Pin 3 (Clock). Connect LEDs with current-limiting resistors to Pin 5 (Q) and Pin 6 (Q̄). The top switch controls Data, the bottom switch controls Clock.

  4. Initial State: Both Switches Off

    Start with both switches in the OFF position (to the left). The clock is LOW and the data input is LOW. Observe the LED outputs—they show the flip-flop's current stored state (which depends on power-up conditions). In this case, the output is showing Q=0, Q̄=1 (right LED on).

  5. Set Data HIGH, Clock Still LOW

    Move the top switch to ON (Data = HIGH), keeping the bottom switch OFF (Clock = LOW). Even though D is now HIGH, the output doesn't change! This demonstrates that the flip-flop only responds to clock edges, not steady states. The D input is being ignored because no clock edge has occurred.

  6. Return Data to LOW

    Move the top switch back to OFF (Data = LOW). The output still hasn't changed—it's still holding the previous state. The flip-flop is truly "remembering" and ignoring the input.

  7. Clock the Data: Rising Edge Capture

    Now set Data HIGH again, then move the Clock switch to ON. This creates a rising edge (LOW to HIGH transition) on the clock. The flip-flop captures the D input value at this exact moment! The output changes to Q=1, Q̄=0 (left LED on). The data has been "clocked in" and stored.

  8. Clock Returns LOW: Data Held

    Move the Clock switch back to OFF while keeping Data HIGH. The output remains at Q=1—the flip-flop has stored the value and continues to hold it even after the clock goes LOW. This is the "memory" behavior.

  9. Change Data: Output Unchanged

    Move the Data switch to OFF (D = LOW). The output stays at Q=1! Even though the data input changed, no clock edge occurred to capture the new value. The flip-flop maintains its stored state.

  10. Rising Edge with Data LOW

    Keep Data LOW and move Clock to ON (rising edge). Now the flip-flop captures D=0, and the output changes to Q=0, Q̄=1. You've successfully clocked in a zero!

  11. Another Rising Edge Test

    Practice more: Set Data HIGH, then create another rising edge by toggling Clock OFF then ON. The output changes to Q=1. The flip-flop reliably captures whatever value is on D at each rising clock edge.

  12. Final State Verification

    Return both switches to OFF. The last captured value remains stored. You've demonstrated that the D flip-flop truly acts as a 1-bit memory cell that only updates when triggered by a rising clock edge.

Challenges

  • Try using the Preset and Clear inputs—what happens when you pull them LOW?
  • Build a toggle flip-flop by connecting Q̄ to D (the output toggles with each clock pulse)
  • Create a simple 2-bit shift register using both flip-flops in the IC
  • Add a debounce circuit to the clock switch for cleaner edge detection
  • Use the second flip-flop to build a 2-bit counter