Bus Architectures

Buses are the communication highways of a digital system, connecting the CPU, memory, and I/O devices. A shared bus uses tri-state buffers to allow multiple devices to drive the same wires (one at a time). Bus protocols and arbitration determine who gets to communicate and when. Understanding bus architecture is essential for connecting your CPU to the outside world.

Objectives

• Explain shared bus architecture and why tri-state buffers are needed
• Describe the three bus types: data bus, address bus, and control bus
• Understand bus arbitration: master/slave, priority, and round-robin
• Compare single-bus and multi-bus architectures
• Identify standard buses: AHB, APB, Wishbone, AXI

Key Takeaways

• Buses connect CPU, memory, and I/O via shared wires
• Three buses: data (bidirectional), address (to slave), control (handshake)
• Tri-state buffers prevent bus contention (only one driver at a time)
• Arbitration: master requests bus, arbiter grants access
• Bus bandwidth = width × frequency; actual throughput is lower

Applications

• ARM AMBA (AHB/APB/AXI): Standard on-chip bus protocols for SoC design.
• Wishbone Bus: Open-source bus for FPGA SoC designs.
• PCI/PCIe: Computer expansion bus connecting GPUs, NICs, and SSDs.
• I2C and SPI: Simple serial buses connecting sensors and peripherals.

Practice Problems

Problem 1: A CPU has a 16-bit address bus and 8-bit data bus. How many devices can it address, and how much data moves per transfer?

Problem 2: Why can't two devices drive a shared bus simultaneously?

Problem 3: DMA controller and CPU both want the bus. CPU has higher priority. What happens?

Problem 4: A system uses a 32-bit data bus at 100 MHz. What is the peak bus bandwidth?