Clock Distribution

In synchronous digital systems, every flip-flop must receive the same clock signal at (ideally) the same time. In reality, different path lengths and loading cause clock skew—differences in clock arrival times. Clock jitter adds random variation. Managing these imperfections is essential for reliable high-speed design.

Objectives

• Define clock skew and clock jitter
• Explain how skew affects setup and hold timing
• Describe clock tree synthesis and H-tree distribution
• Understand PLL and DLL for clock generation and deskewing
• Calculate timing impact of clock skew on slack

Key Takeaways

• Clock skew = difference in clock arrival times at flip-flops
• Jitter = random variation in clock edges, reduces timing margin
• Clock trees and H-trees minimize skew through symmetric distribution
• PLLs and DLLs clean up and multiply clock signals
• Skew and jitter must be accounted for in timing analysis

Applications

• ASIC Design: Clock tree synthesis is a critical step in chip physical design.
• FPGA Clocking: Built-in PLLs and global clock networks manage distribution.
• Multi-Chip Systems: Clock distribution across PCBs requires careful trace matching.
• High-Speed Interfaces: SerDes links use clock recovery from data.

Practice Problems

Problem 1: Two flip-flops receive the clock with 1 ns skew. Original setup slack was 2 ns. What is the new slack if the receiving FF gets the clock 1 ns late?

Problem 2: A clock has 200 ps of jitter. How much does this reduce the effective setup margin?

Problem 3: Why is an H-tree better than a linear chain for clock distribution?

Problem 4: A PLL has input frequency 10 MHz and multiplication factor 20. What is the output frequency?