D Flip-Flop

The D (Data) flip-flop is the most widely used sequential element. It captures the value of the D input at the moment of a clock edge (usually rising edge) and holds that value until the next clock edge. Unlike the SR latch, it has no forbidden state - whatever value is on D when the clock ticks gets stored. D flip-flops are the building blocks of registers, counters, and state machines.

Objectives

• Understand positive and negative edge triggering
• Read timing diagrams: setup time, hold time, clock-to-Q delay
• Describe the master-slave implementation
• Use the 74HC74 dual D flip-flop
• Apply D flip-flops in register and counter circuits

Key Takeaways

• D flip-flop captures D at the clock edge and holds it until the next edge
• No forbidden state - any value on D is valid
• Setup time: D must be stable before clock edge. Hold time: stable after edge.
• Violating timing → metastability (undefined output)
• 74HC74: dual positive-edge D flip-flop with preset and clear
• Master-slave architecture creates edge-triggered behavior from two latches

Applications

• Registers: Groups of D flip-flops store multi-bit data.
• Counters: Connected with feedback to count clock pulses.
• State Machines: Store current state in FSM designs.
• Pipeline Stages: Hold intermediate values between computation stages.

Practice Problems

Problem 1: A positive-edge D flip-flop has D=1 and CLK transitions from LOW to HIGH. What happens to Q?

Problem 2: If setup time is 20ns and the clock period is 100ns, how long before the clock edge must D be stable?

Problem 3: How do you build a toggle flip-flop (T flip-flop) from a D flip-flop?

Problem 4: What is metastability and when does it occur?