Dynamic RAM (DRAM)

The 1T-1C DRAM cell, refresh cycles, and how DRAM serves as main system memory.

Dynamic RAM stores each bit as charge on a tiny capacitor, accessed through a single transistor. This 1T-1C cell is much smaller than SRAM's 6T cell, enabling very high density. However, the capacitor charge leaks over time, requiring periodic refresh. DRAM forms the main memory (RAM) in virtually all computers and mobile devices.

Objectives

  • Explain the 1T-1C DRAM cell and charge storage mechanism
  • Describe why DRAM needs periodic refresh and how refresh works
  • Understand row/column address multiplexing (RAS/CAS)
  • Compare DDR generations (DDR3, DDR4, DDR5)
  • Calculate DRAM bandwidth and latency

Key Takeaways

  • 1T-1C cell: much smaller than SRAM, enabling high density
  • Charge leaks; periodic refresh required every 64 ms
  • Read is destructive; must restore data after every read
  • DDR SDRAM transfers data on both clock edges
  • Main system memory uses DRAM (GB capacity at reasonable cost)

Applications

  • Computer Main Memory: DDR4/DDR5 DIMMs provide gigabytes of system RAM.
  • Mobile Devices: LPDDR5 provides high bandwidth at low power.
  • Graphics Cards: GDDR6/GDDR7 specialized DRAM for GPU framebuffers.
  • Servers: ECC DRAM with error correction for reliability.

Practice Problems

Problem 1: A DRAM chip has 8 Gb capacity with 1T-1C cells. How many transistors and capacitors?

Problem 2: DDR4-3200 has a data rate of 3200 MT/s with a 64-bit bus. What is the peak bandwidth?

Problem 3: Why is a DRAM read destructive while an SRAM read is not?

Problem 4: How many refresh operations per second for a 64 ms refresh interval with 8192 rows?