FPGA Architecture

Inside an FPGA: lookup tables, configurable logic blocks, routing, I/O blocks, and hard IP.

An FPGA (Field-Programmable Gate Array) is a sea of configurable logic blocks connected by a programmable routing network. Each logic block contains lookup tables (LUTs) that can implement any Boolean function, flip-flops for sequential logic, and carry chains for arithmetic. Understanding FPGA architecture is key to writing efficient HDL code and achieving timing closure.

Objectives

  • Describe the three main FPGA components: CLBs, routing, and I/O
  • Explain how a LUT implements any combinational function
  • Understand the role of carry chains, block RAM, and DSP slices
  • Compare SRAM-based and flash-based FPGA technologies
  • Read FPGA datasheets and understand resource utilization

Key Takeaways

  • LUTs implement any Boolean function by storing its truth table
  • CLBs contain LUTs + flip-flops + carry chains
  • Routing (programmable interconnect) consumes ~80% of FPGA area
  • Hard IP (BRAM, DSP, PLLs) provides optimized dedicated resources
  • SRAM-based FPGAs need external configuration; flash-based are instant-on

Applications

  • Digital Signal Processing: DSP slices provide hardware multipliers for filters and transforms.
  • High-Speed Networking: Transceivers enable multi-gigabit serial links.
  • Video Processing: Block RAM buffers video frames; LUTs process pixels.
  • Custom Processors: Soft CPU cores (MicroBlaze, RISC-V) implemented in LUTs.

Practice Problems

Problem 1: A 4-input LUT stores how many configuration bits?

Problem 2: An FPGA has 50,000 6-LUTs. Approximately how many equivalent NAND gates is this?

Problem 3: Why does routing consume most of the FPGA area?

Problem 4: What advantage does a flash-based FPGA have over SRAM-based?