FPGA Design Flow

The FPGA design flow transforms a hardware description (written in Verilog or VHDL) into a bitstream that configures the FPGA. The flow includes simulation for verification, synthesis to convert HDL to logic, place-and-route to map logic onto the physical FPGA, and timing analysis to ensure the design works at the target clock frequency.

Objectives

• List the steps in the FPGA design flow from specification to bitstream
• Explain what synthesis does (HDL → netlist)
• Understand place-and-route and its impact on timing
• Describe simulation at behavioral, post-synthesis, and post-layout levels
• Use timing constraints to guide the tools

Key Takeaways

• Flow: HDL → Simulation → Synthesis → Place-and-Route → Bitstream
• Simulation verifies correctness at behavioral and post-layout levels
• Synthesis converts HDL to a netlist of LUTs, FFs, and primitives
• Place-and-route maps the netlist to physical FPGA resources
• Timing constraints guide the tools; negative slack = design fails

Applications

• Xilinx/AMD Vivado: Industry-standard tool for Xilinx FPGAs.
• Intel Quartus Prime: Design suite for Intel/Altera FPGAs.
• Open-Source Tools: Yosys (synthesis) + nextpnr (place-route) for Lattice and others.
• IP Integration: Pre-built IP cores (PCIe, DDR controller) speed development.

Practice Problems

Problem 1: Your design compiles but simulation shows incorrect output. Where in the flow is the bug?

Problem 2: Post-route timing report shows -0.5 ns slack on a path. What does this mean?

Problem 3: Synthesis reports 85% LUT utilization. Is this a concern?

Problem 4: What is the difference between behavioral and post-route simulation?