Instruction Set Architecture

The Instruction Set Architecture (ISA) is the contract between hardware and software—it defines what instructions the CPU understands, how they are encoded in binary, and how operands are specified. Designing a good ISA means balancing simplicity (easy to decode in hardware) with expressiveness (useful operations for programmers). The ISA is the most important architectural decision in CPU design.

Objectives

• Define the ISA and its role as the hardware-software interface
• Design instruction encoding formats (opcode, operands)
• Explain common addressing modes (immediate, register, direct, indirect)
• Write simple assembly language programs
• Compare fixed-length and variable-length instruction formats

Key Takeaways

• ISA = the hardware-software contract defining instructions and encoding
• Opcode identifies operation; operand fields specify data sources
• Addressing modes: immediate, register, direct, indirect, indexed
• RISC: fixed-length, load-store, many registers, simple decode
• CISC: variable-length, register-memory, complex instructions

Applications

• ARM Architecture: RISC ISA dominating mobile, embedded, and increasingly server markets.
• x86 Architecture: CISC ISA powering desktop and server computing for 40+ years.
• RISC-V: Open-source ISA enabling custom processor design and education.
• Compiler Design: Compilers must generate efficient code targeting the ISA.

Practice Problems

Problem 1: Design a 16-bit instruction format for a CPU with 16 instructions and 4 registers. How many bits for opcode, source, destination?

Problem 2: What addressing mode is: LOAD R3, [R1 + 8]?

Problem 3: Write a simple assembly sequence to compute R3 = R1 + R2 × 4 (assuming multiply exists).

Problem 4: Why do RISC architectures prefer fixed-length instructions?