Introduction to Verilog

Verilog is a Hardware Description Language (HDL) used to describe digital circuits in text form. Unlike software programming, Verilog describes hardware that operates in parallel—all modules run simultaneously. This introduction covers the essential Verilog constructs needed to describe combinational and sequential logic for FPGA implementation.

Objectives

• Write a Verilog module with inputs, outputs, and internal signals
• Use assign statements for combinational logic
• Use always blocks for both combinational and sequential logic
• Understand the difference between wire and reg types
• Write a simple testbench to verify a Verilog design

Key Takeaways

• Verilog describes hardware (parallel), not software (sequential)
• module = basic building block with ports
• assign = continuous combinational logic; always @(*) = procedural combinational
• always @(posedge clk) = sequential logic (flip-flops)
• Use non-blocking (<=) for sequential, blocking (=) for combinational

Applications

• FPGA Design: Primary language for Xilinx, Intel, Lattice FPGA development.
• ASIC Design: Verilog RTL is synthesized into silicon chip designs.
• Verification: SystemVerilog extends Verilog with powerful testbench features.
• Open-Source Hardware: RISC-V processors and other open designs use Verilog.

Practice Problems

Problem 1: Write Verilog for a 2-input AND gate.

Problem 2: Write a D flip-flop with synchronous reset.

Problem 3: What is wrong with: always @(posedge clk) y = a & b; ?

Problem 4: Why can Verilog describe parallel hardware but C code runs sequentially?