Pipelining

Pipelining is the technique that made modern CPUs fast. Instead of completing one instruction before starting the next, a pipelined CPU overlaps execution—while one instruction is being executed, the next is being decoded, and the one after that is being fetched. Like an assembly line, each stage handles a different instruction simultaneously, dramatically increasing throughput without making any single instruction faster.

Objectives

• Explain the pipeline concept using the assembly line analogy
• Describe the classic 5-stage RISC pipeline (IF, ID, EX, MEM, WB)
• Identify data hazards, control hazards, and structural hazards
• Apply forwarding (bypassing) to resolve data hazards
• Understand pipeline stalls and their performance impact

Key Takeaways

• Pipelining overlaps instruction execution for ~N× throughput (N stages)
• Classic 5-stage: Instruction Fetch, Decode, Execute, Memory, Write-Back
• Data hazards: resolved by forwarding; load-use requires one stall
• Control hazards: branch prediction reduces misprediction penalties
• Deeper pipelines increase throughput but amplify hazard penalties

Applications

• ARM Cortex-M: 3-stage pipeline in microcontrollers for embedded systems.
• RISC-V Implementations: Classic 5-stage pipeline in educational and production RISC-V cores.
• Intel/AMD CPUs: 14-20+ stage pipelines with out-of-order execution and speculation.
• GPU Pipelines: Deep pipelines process thousands of threads to hide latency.

Practice Problems

Problem 1: A 5-stage pipeline executes 1000 instructions. How many cycles does it take (no hazards)?

Problem 2: ADD R1,R2,R3 followed by SUB R4,R1,R5. What hazard exists and how is it resolved?

Problem 3: LOAD R1,[R2] followed by ADD R3,R1,R4. Can forwarding fully eliminate the stall?

Problem 4: A 12-stage pipeline has branch misprediction penalty of 11 cycles. If 15% of instructions are branches with 10% misprediction rate, what is the CPI?