Propagation Delay

Understanding gate delays, critical paths, and how propagation delay limits circuit speed.

Every logic gate takes a finite amount of time to respond to its inputs. This propagation delay—typically nanoseconds—determines how fast a digital circuit can operate. Understanding propagation delay is essential for designing reliable high-speed circuits and calculating maximum clock frequencies.

Objectives

  • Define propagation delay (tpd), rise time, and fall time
  • Distinguish between tpLH and tpHL
  • Calculate total delay through cascaded gates
  • Identify the critical path in a combinational circuit
  • Read timing specifications from IC datasheets

Key Takeaways

  • Every gate has a non-zero propagation delay (tpd)
  • tpLH and tpHL may differ; average gives tpd
  • Critical path = longest delay path, sets maximum speed
  • Fan-out and wiring add to delay
  • Datasheet timing specs are essential for design

Applications

  • Clock Frequency Selection: Maximum clock speed is limited by the critical path delay.
  • Pipeline Stage Balancing: Each pipeline stage must complete within one clock period.
  • High-Speed Serial Links: Controlled delay matching ensures signal integrity.
  • FPGA Timing Closure: Meeting timing constraints is a key step in FPGA design.

Practice Problems

Problem 1: A NOT gate has tpd = 3 ns, an AND gate has tpd = 5 ns. What is the total delay of NOT → AND → NOT?

Problem 2: A circuit has two paths: Path A through 4 gates (3+5+3+4 = 15 ns) and Path B through 3 gates (5+5+5 = 15 ns). What is the critical path delay?

Problem 3: If tpLH = 8 ns and tpHL = 12 ns, what is the average propagation delay?

Problem 4: A 4-bit ripple carry adder uses full adders with 10 ns carry delay each. What is the worst-case delay?