Setup and Hold Times

Flip-flops require their data input to be stable for a minimum time before the clock edge (setup time) and after the clock edge (hold time). Violating these constraints causes metastability—an unpredictable state that can propagate errors through an entire system. Understanding setup and hold times is critical for reliable synchronous design.

Objectives

• Define setup time (tsu), hold time (th), and clock-to-output delay (tco)
• Explain why timing violations cause metastability
• Calculate timing slack (positive = safe, negative = violation)
• Determine maximum clock frequency from timing parameters
• Design circuits that avoid timing violations

Key Takeaways

• Setup time: data stable before clock edge; hold time: stable after
• Violations cause metastability (unpredictable output)
• Setup slack determines maximum frequency
• Hold violations are independent of clock frequency
• Synchronizer chains protect against metastability from asynchronous inputs

Applications

• FPGA Timing Closure: Meeting setup and hold constraints across all paths.
• Clock Domain Crossing: Synchronizers prevent metastability between clock domains.
• PCB Design: Trace length matching ensures hold time compliance.
• Memory Interfaces: DDR SDRAM requires precise setup/hold timing for data and address buses.

Practice Problems

Problem 1: A flip-flop has tsu = 2 ns, th = 1 ns, tco = 3 ns. Logic between two flip-flops has tpd = 8 ns. What is the minimum clock period?

Problem 2: With tco = 3 ns, minimum logic delay = 2 ns, and th = 1 ns, is hold time met?

Problem 3: Why do synchronizer chains use 2 or 3 flip-flops instead of just 1?

Problem 4: A system runs at 100 MHz. Flip-flop tco = 2 ns, tsu = 1.5 ns. What is the maximum combinational logic delay allowed?