SR Latch

The SR (Set-Reset) latch is the most basic memory element in digital electronics. Made from two cross-coupled NOR or NAND gates, it can store one bit of data. The "Set" input forces the output to 1, the "Reset" input forces it to 0, and when both inputs are inactive, the latch remembers its previous state. This feedback mechanism is the foundation of all sequential circuits.

Objectives

• Build an SR latch from NOR gates and from NAND gates
• Write the truth table including the forbidden/invalid state
• Understand the cross-coupled feedback mechanism
• Draw timing diagrams for SR latch operation
• Explain why the S=R=1 state is problematic
• Describe the gated SR latch with enable input

Key Takeaways

• SR latch: the simplest 1-bit memory element from cross-coupled gates
• NOR version: active-HIGH inputs. NAND version: active-LOW inputs
• Set (S): forces Q=1. Reset (R): forces Q=0. Both inactive: hold (memory)
• S=R=active simultaneously is the FORBIDDEN state (undefined output)
• Gated SR latch adds enable control for when state changes are allowed
• Foundation for all flip-flops and sequential circuits

Applications

• Switch Debouncing: SR latches clean up noisy mechanical switch signals.
• Control Flags: Set/reset flags in control systems.
• Alarm Circuits: Latching alarm that stays active until manually reset.

Practice Problems

Problem 1: An SR latch is in the Reset state (Q=0). What happens when S goes HIGH then back LOW?

Problem 2: Why is S=R=1 called the "forbidden" state in a NOR SR latch?

Problem 3: Convert a NOR SR latch to use NAND gates. How do the input polarities change?

Problem 4: How does a gated SR latch differ from an ungated one?