Static RAM (SRAM)

The 6-transistor SRAM cell, read/write operations, and use in caches and register files.

Static RAM stores each bit using a cross-coupled latch (6 transistors), retaining data as long as power is applied without needing refresh. SRAM is the fastest type of semiconductor memory, making it ideal for CPU caches, register files, and on-chip buffers. Understanding SRAM is foundational to memory system design.

Objectives

  • Explain the 6T SRAM cell structure and how it stores a bit
  • Describe read and write operations with wordlines and bitlines
  • Understand the stability constraints (read disturb, write margin)
  • Compare SRAM with DRAM in terms of speed, density, and cost
  • Identify SRAM applications in cache hierarchies

Key Takeaways

  • 6T SRAM cell: cross-coupled inverters + 2 access transistors
  • No refresh needed (static)—data held as long as power is on
  • Fastest semiconductor memory (1–10 ns access)
  • Lower density and higher cost than DRAM (6T vs 1T-1C per bit)
  • Used for CPU caches, register files, and on-chip buffers

Applications

  • CPU Cache (L1/L2/L3): Fast SRAM stores frequently accessed data close to the processor.
  • Register Files: CPU registers are implemented as small, fast SRAM arrays.
  • Networking Buffers: Router and switch packet buffers use SRAM for speed.
  • FPGA Configuration: SRAM-based FPGAs store configuration in SRAM cells.

Practice Problems

Problem 1: How many transistors does a 64 KB SRAM require (6T cells)?

Problem 2: Why is SRAM faster than DRAM?

Problem 3: During a read operation, what prevents the read from destroying the stored value?

Problem 4: A CPU has 32 KB L1 cache and 256 KB L2 cache. How much SRAM is needed?