State Table Design

Designing an FSM in hardware follows a systematic process: define states and transitions, create a state table, assign binary codes to states, derive next-state and output equations using K-maps, and implement with flip-flops and combinational logic. This topic walks through the complete design procedure.

Objectives

• Create a state table from a state diagram
• Assign binary encodings to states
• Derive next-state equations using K-maps
• Use flip-flop excitation tables for D, JK, and T flip-flops
• Implement a complete FSM design in hardware

Key Takeaways

• FSM design: state diagram → state table → state assignment → equations → circuit
• D flip-flop excitation: D = Q_next (simplest mapping)
• Binary encoding minimizes flip-flops; one-hot minimizes logic complexity
• K-maps derive next-state and output equations from the state table
• Unused states should be handled (force return to valid state for safety)
• Always verify the final circuit against the original specification

Practice Problems

Problem 1: A 2-bit up counter has states S0(00), S1(01), S2(10), S3(11) and cycles S0→S1→S2→S3→S0. Derive the D flip-flop equations.

Problem 2: How many flip-flops for a state machine with 6 states?

Problem 3: What are the advantages of one-hot encoding vs. binary encoding?

Problem 4: For a D flip-flop, what is the excitation equation to transition from Q=0 to Q=1?