Timing Hazards

Even when logic is functionally correct, unequal propagation delays through different paths can cause momentary incorrect outputs called glitches or hazards. In combinational circuits, these hazards produce brief spurious pulses that can trigger downstream flip-flops or cause system errors. Understanding and eliminating hazards is essential for glitch-free design.

Objectives

• Define static-1, static-0, and dynamic hazards
• Identify hazards using Karnaugh maps
• Eliminate static hazards by adding redundant terms
• Understand when hazards matter and when they are harmless
• Recognize hazard-free design techniques

Key Takeaways

• Hazards are glitches caused by unequal path delays, not logic errors
• Static hazards: output should stay constant but momentarily changes
• K-map analysis reveals static hazards (adjacent uncovered groups)
• Adding consensus terms (redundant logic) eliminates static hazards
• In synchronous designs, hazards are usually harmless

Applications

• Asynchronous Circuit Design: Hazard-free design is mandatory for clockless circuits.
• Clock Generation Logic: Glitches in clock paths can cause catastrophic timing errors.
• Set/Reset Logic: Glitches on SR latch inputs cause unexpected state changes.
• Level-Sensitive Designs: Latch-based designs are vulnerable to hazards during transparent phase.

Practice Problems

Problem 1: F = AB + A'C. When A transitions from 1→0 with B=1, C=1, why might a glitch occur?

Problem 2: What term would you add to F = AB + A'C to eliminate the static-1 hazard?

Problem 3: In a fully synchronous design, why are combinational hazards usually acceptable?

Problem 4: A circuit with 3 levels of logic has paths with delays 5 ns, 8 ns, and 12 ns. Could this exhibit a dynamic hazard?